1. Field of the Invention
The present invention relates to a technology for analyzing delay occurring of a circuit.
2. Description of the Related Art
Recently, in very large scale integration (VLSI) manufacturing, influence of statistical factors, for example, of process variation, is increasing due to fragmentation of processes. A technology for decreasing delay considering the influence of statistical factors is required in VLSI designing to obtain high yield in creating circuits that have required performance. Conventionally, a statistical delay analysis method is developed that considers process variation and eliminates unnecessary delay margin (for example, Japanese Patent Laid-Open Publication No. 2004-252831). Furthermore, a delay minimizing device is developed that minimizes delay of a logic circuit (for example, Japanese Patent Laid-Open Publication No. H7-334530).
However, in the conventional technology, it is difficult to accurately deal with statistical factors. For example, when dealing with statistical factors in a conventional static timing analysis (STA), values of the statistical factors are estimated based on the worst case scenario, thereby resulting in unrealistic and inaccurate values of circuit delay. This leads to a repetition of circuit designing, thereby increasing the burden on a designer, and causing further delay in designing time.
Carrying out a delay analysis of all paths in a chip by using such conventional technology greatly increases the processing time of the delay analysis, thereby further increasing the designing time. In the above conventional technology, circuit delay is minimized at a logical level called partial collapsing. Thus, circuit delay is minimized without carrying out a timing analysis. In other words, because circuit delay is minimized without considering a delay of critical paths, an accurate circuit delay cannot be estimated.